1. Field of the Invention
The present invention relates to a semiconductor device that uses a multi-finger (comb-shaped) metal oxide semiconductor (MOS) transistor as an electrostatic discharge (ESD) protection element.
2. Description of the Related Art
In semiconductor devices including MOS transistors, it is a known practice to install an “off” transistor as an ESD protection element for preventing breakdown of an internal circuit due to static electricity from a terminal for an external connection (PAD). The “off” transistor is an N-MOS transistor that is kept in an off state by fixing the electric potential of the gate to the ground level (Vss).
The off transistor is formed of a transistor having a wide gate width of about several hundreds of microns because, unlike other MOS transistors that constitute internal circuits such as a logic circuit, the off transistor is required to allow a large amount of current generated by static electricity to flow instantaneously.
A common way for the off transistor to reduce the occupation area is to adopt a multi-finger type form in which a plurality of drain regions, a plurality of source regions, and a plurality of gate electrodes are combined in a comb-shaped pattern.
However, the structure which is a combination of a plurality of transistors makes it difficult to ensure that all parts of the ESD protection MOS transistor operate uniformly, which can lead to a concentration of current in, for example, a place at a short distance from the external connection terminal, or a place where the sum of wiring resistance and resistance between wiring lines is small. The concentration of current causes a local concentration of stress, which in turn triggers a breakdown, without giving the ESD protection MOS transistor a chance to fully exert its intended ESD protection function.
An improvement for this has been proposed in which uniform operation among transistors is accomplished by varying an aspect of the transistors depending on the distance from the external connection terminal or from substrate contacts, specifically, by making salicide blocks in drain regions which prevent silicidation progressively longer as the distance from the substrate contacts increases (see JP 2007-116049 A, for example).
However, reducing the gate width in an attempt to, for example, ensure uniform operation throughout the off transistor renders the off transistor incapable of implementing its protection function satisfactorily. JP 2007-116049 A aims to adjust the transistor operation speed locally by adjusting the distance from the salicide block in a drain region which prevents silicidation to a gate electrode in accordance with the distance from the substrate contacts, and thus controlling the length of a high resistance region. A problem of JP 2007-116049 A, which is characterized by making the salicide block length progressively shorter as the distance to the substrate contacts decreases, is that, in a part close to the external connection terminal, the off transistor has a small resistance between a gate electrode and salicide metal in a drain region due to its salicide block length, and consequently fails to operate over the entire gate electrode width of the off transistor, which causes a one-point-concentrated breakdown in the part close to the external connection terminal.
The failure to operate over the entire gate electrode width of the off transistor has become particularly problematic in recent years, where the development of wiring containing high-melting point metal and the resultant lowering of wiring resistance have brought about a further increase in surge propagation speed which, contrary to expectations, causes a surge to concentrate on salicide regions in some of drain regions. In the case where the salicide blocks in drain regions are at a constant distance from gate electrodes, too, there is a problem in that an overconcentrated breakdown occurs in a part of an area between a gate electrode and a drain that is close to the external connection terminal. FIG. 5 is a micrograph in which a breakdown point in an off transistor is identified after a breakdown due to the application of an ESD surge. An area surrounded by a circle in FIG. 5 indicates the point where the breakdown has occurred due to the application of the surge. As shown in FIG. 5, the off transistor suffered a local breakdown in a part of an area between a gate electrode and a drain that is close to the external connection terminal.